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DesignCon 2006

Dates: February 6 – 9 2006
Location: Santa Clara Convention Center; Santa Clara, California USA
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Table of Contents

TecForums
TF-MA1 Thermal Issues in Board Design
John Wilson, Flomerics, Inc
TF-MA2 Introduction to IBIS 4.1 AMS SERDES Driver Modeling, and Other Novel Applications of AMS Modeling
Gary Pratt, Manager, High-Speed Partnerships, Mentor Graphics
TF-MA3 The State of IEEE 802.3ap Backplane Ethernet
John D'Ambrosia, Manager, Semiconductor Relations, Tyco Electronics
Adam Healey, Distinguished Member of Technical Staff, Agere Systems
TF-MA4 Measurement-Based Signal-Integrity Analysis of Passive Physical Layer
Dima Smolyansky, Tektronix, Inc.
TF-MA5 Practical Guidance in Achieving Design Portability
Doug Amos, Director, European Business Development, Synplicity
Javier Orensanz, ARM
Tim Daniels, Manager, Technical Product Marketing, LSI Logic, Europe
TF-MP1 Beyond RTL: Advanced Digital System Design
Rishiyr Nikhil, Chief Technology Officer, Bluespec, Inc.
TF-MP2 Opening Closed Eyes: Analysis and Equalization of High-Data-Rate Signals on Buses and Backplanes
Ransom Stephens, Research Scientist, Teraspeed Consulting Group
TF-MP3 Comparison of Power Distribution Network Design Methods
Dale Becker, Senior Technical Staff Member, IBM
Istvan Novak, Senior Staff Engineer, SUN Microsystems
Larry D. Smith, SUN Microsystems
Steve Weir, Teraspeed Consulting Group
TF-MP4 Recent Developments in Jitter and Signal-Integrity Measurement and Analysis
Mike Li, Chief Technology Officer, Wavecrest
TF-MP5 From Algorithm to Low-Power Implementation: Optimizing a Ghost Canceling Design for Low Power
Frank Schirrmeister, ChipVision Design Systems
Jan Jezek, Design Engineer, ChipVision Design Systems
Eike Schmidt, Chief Architect, ChipVision Design Systems
TF-THA1 Getting Started with SystemVerilog Assertions
Stuart Sutherland, Lead Engineer, Sutherland HDL, Inc.
TF-THA2 Embedded Capacitance and Embedded Capacitors: Overview on Modeling and Applications
Jun Fan, NCR
Zhiping Yang, Principal Integrity Engineer, Apple Computer
Istvan Novak, Senior Staff Engineer, Sun Microsystems
Todd H. Hubing, Professor, University of Missouri-Rolla
James L. Drewniak, Professor, University of Missouri-Rolla
Joel S. Peiffer, Lead Engineering Specialist, 3M
TF-THA3 Multi-Mode, Multi-Corner, Multi-Voltage, Multi-Frequency Design: When, How, and Why
Pradeep Fernandes, Vice President, Product Engineering, Cadence Design Systems
Tony Young, Core Competency, Senior Technical Leader, Cadence Design Systems
Christina Chu, Principal Product Engineer, Cadence Design Systems
Track 1 | Application-Specific Design
1-TA1 A Fast Methodology for Static Power IP Characterization
Peter H. Chen, Senior Project Manager, Faraday Technology Corporation
Sammy Lee, Faraday Technology Corporation
Jim H. Wang, Faraday Technology Corporation
Peter Pong, Faraday Technology Corporation
Harrison Liu, Faraday Technology Corporation
Alvin Chen, Faraday Technology Corporation
1-TA2 Low-Power Transport Stream Demultiplexer Architecture with New Secure Format to Remultiplexing Approach
Jalaj Jain, Senior Director, Engineering, Metta Semiconductor
Pravin Desale, ASIC Director, Metta Semiconductor
1-TA3 Design of a 400MHZ DDR2 Memory Controller for a High-Performance CPU Application
Warren Miller, Ingot Systems
Raghavan Menon, Ingot Systems
1-TA4 Designing a Real-Time HDTV 1080p Baseline H.264/AVC Encoder Core
Vincenzo Liguori, Ocean Logic Pty Ltd.
Kevin Wong, Ocean Logic Pty Ltd.
1-TP1 Ultra-Low-Power Design in Cost-Constrained Deeply Embedded Systems
Mark Buccini, Marketing Director, Advanced Embedded Controllers, Texas Instruments
1-TP2 Hardware Firmware Partitioning of the WiMedia Ultra-Wideband MAC Based on Performance Analysis
Debashis Goswami, Technical Manager, MindTree Consulting Pvt Ltd.
Vivek Padi, Design Engineer, MindTree Consulting Pvt Ltd.
Santosh Hegde, Design Engineer, MindTree Consulting Pvt Ltd.
1-WA1 Back-End Methodology and Techniques for a Multi-Protocol Mixed Signal IP Design
Ken Umino, Design Consultant, Synopsys
John Stonick, Scientist and R&D Engineer, Synopsys
Bill Beale, CAE, Synopsys
Ross Segelken, R&D Engineer, Synopsys
Jason Upton, R&D Engineer, Synopsys
1-WA2 Application Lambda Switching (A New Application for All-Optical Networking Technology)
Victor Rychlicki, President, Rychtronix Mind Werkz
Track 2 | Chip-Level Functional Design
2-TA2 Reuse or Recycling? A Practical Approach for Designers
Michael Lee, HDS Group Manager, Mentor Graphics
Tom Dewey, Technical Marketing Engineer, Mentor Graphics
2-TA3 A Taxonomy for the Electronic System Level (ESL)
Brian Bailey, Consultant, Brian Bailey Consulting
2-TA4 Complex Clock and Reset Issues, and How Platform ASICs Address Them
Greg Martin, Senior Product Applications Engineer, LSI Logic
Jonathan Byrn, Design Methodology Engineer, LSI Logic
Grant Lindberg, Director of Marketing Applications, LSI Logic
2-TP1 Tricks and Techniques for Implementing High-Performance PCI-Express Interfaces in FPGAs and ASICs
Warren Miller, Ingot Systems
Pushkar Upadhye, Ingot Systems - Pune, India
2-TP2 Leveraging System-C Transaction-Level Models for Architectural Exploration, Algorithm Development, and Large Configuration Evaluation
Terry Doherty, Principle Engineer, Emulex
2-WP1 A Comparative Study on the Effectiveness of Automated Assertions in a Project Design Flow
Andreas Meyer, Chief Technical Officer, Assertive Design
2-WP2 Why Did My Chip Do That?: A Survey of On-Chip Debug and Diagnosis Techniques
G. Carina Chiang, RedBear Technology
Brian Bailey, Consultant, Brian Bailey Consulting
Track 3 | Functional Verification
3-TA1 Why Is My Customer a Better Verification Engineer than Me?
Alfonso Iniguez, Verification Engineering, Freescale Semiconductor
3-TA2 Automated Risk Elimination by Formally Critiquing Verification Plan and Design Documentation
Jeff Li, Superior Logic Corporation
3-TA3 Functional Verification of a Multi-Gigabit Transceiver IP in a FPGA
Ning Xue, Altera Corp.
Ramanand Venkata, Altera Corporation
Arch Zaliznyak, Altera Corporation
Divya Vijayaraghavan, Altera Corporation
Steve Park, Altera Corporation
Chong Lee, Altera Corporation
Rakesh Patel, Altera Corporation
3-TA4 A Multiparadigm Verification Flow
Dave Whipp, Verification Architect, NVIDIA
3-TP1 Leveraging Assertions in SystemVerilog Testbench to Get to Closure
Leena Singh, Cadence Design Systems, Inc.
Tim Pylant, Cadence Design Systems, Inc.
3-TP2 Verification Planning to Functional Closure of Processor-Based SoCs
Andrew Piziali, Cadence Design Systems
3-WA1 Verifying the TriCore2 Multithreaded Microprocessor
Fabio Bruno, Core Verification Manager, Infineon Technologies
Tim Blackmore, Senior Verification Engineer, Infineon Technologies
3-WA2 The ABV Capability Maturity Model
Harry Foster, Chief Methodologist, Jasper Design Automation
3-WP1 Nexus-Based Multicore Debug
Neal Stollon, Systems Engineer, First Silicon Solutions
Rich Collins, IP Manager, Freescale Semiconductor
Track 4 | Chip-Level Physical Design and Verification
4-TA1 Design and Analysis for Variability in Nanometer Technologies
Ajay Bhatia, Manager, SUN Microsystems
Sagar Reddy, Sun Microsystems
Shashank Shastry, Sun Microsystems
4-TA2 New RFIC Design Flow for Voltage Controlled Oscillator (VCO) Circuit Verification
Albert Yen, Mixed-Mode and Radio Frequency Technology Manager, UMC Corporation
Daniel Wu, RF and Mixed-Mode Specialist, Ansoft Corporation
Lawrence Williams, Director, Ansoft Corporation
4-TA3 Manufacturability Studies of X Architecture Diagonal Lines
Kalyan Thumaty, Vice President & General Manager, X Architecture Cadence Design Systems, Inc.
Narain Arora, Vice President of Technology, Cadence Design Systems.
4-TA4 Overcoming Signal-Integrity Issues with Wideband Noise Cancellation Technology
Mike Vrazel, Technical Director, Quellan, Inc.
Andrew Kim, Quellan, Inc
4-TP1 A Framework for Optimal Utilization of Hardware Resources in Complex FPGA Devices
Henry Yu, Principal Engineer, Mentor Graphics
Mandar Chitnis, Development Engineer, Mentor Graphics
Rakesh Jain, Mentor Graphics Corporation
Darren Zacher, Mentor Graphics Corporation
4-TP2 The Impact of DFM in the Design Phase Below 90 nm
Marc Levitt, Vice President, Design for Manufacturing, Cadence Design Systems
Track 5 | Chip and Package Co-Design
5-TP1 Frequency-Dependent Physical-Statistical Material Property Extraction for Tabular W-Element Model Based on VNA Measurements
Dong-Ho Han, Intel Corporation
Myung Joon Choi, Senior SI Engineer, Intel Corporation
Jungwook Suk, Intel Corporation
Woong-Hwan Ryu, Staff Engineer, Intel Corporation
5-TP2 The Myth about the Ground and How to Correctly Use It in High-Speed Signal-Integrity and Power-Integrity Modeling and Simulation
Zhiping Yang, Principal Integrity Engineer, Apple Computer
5-WA1 FPGA Power Sag Noise Analysis in Three Domains: Time, Frequency, and Spectrum
Hong Shi, Altera
Geping Liu, Altera
Alan Liu, Altera
5-WA2 Fast Time-Domain Simulation of 200+ Port S-Parameter Package Models
Vadim Heyfitch, MTS Engineer, Altera Corporation
Gary Pratt, Manager of High-Speed Partnerships, Mentor Graphics
Vladimir Dmitriev-Zdorov, Software Scientist, Mentor Graphics
Sherri Azgomi, Senior Applications Engineer, Altera Corporation
5-WP1 Precision Design, Analysis, and Experimental Verification of an Equalized 10-Gbps Link
Lei Shan, Research Staff Member, IBM T.J. Watson Research Center
Young Kwark, Research Staff Member, IBM T.J. Watson Research Center
Petar Pepeljugoski, Research Staff Member, IBM T.J. Watson Research Center
Mounir Meghelli, Research Staff Member, IBM T.J. Watson Research Center
Troy Beukema, Research Staff Member, IBM T.J. Watson Research Center
Christian Baks, Engineer, IBM T.J. Watson Research Center
Jean Trewhella, Technical Staff, IBM T.J. Watson Research Center
Mark Ritter, Research Staff Member, IBM T.J. Watson Research Center
5-WP2 Impedance Matching Techniques for VLSI Packaging
Brock LaMeres, Hardware Design Engineer, Agilent Technologies
Sunil Kharti, Assistant Professor, Texas A&M University
Kanupriya Gulati, Ph.D. Student, Texas A&M University
Rajesh Garg, Ph.D. Student, Texas A&M University
Track 6 | PCB and Package Technologies
6-TA1 Designing of Printed Circuits using Substrates with Combined Embedded Capacitance and Resistance for Better Electrical Performance and Higher Integration
John Andresakis, Vice President of Strategic Technology, Oak-Mitsui Technologies
Pranabes Pramanik, Oak-Mitsui Technologies
Daniel Brandler, Ohmega Technologies, Inc.
Dong Nong, Ohmega Technologies, Inc.
6-TA2 Impedance Characterization and Design Optimization of PCB Embedded Passive Components
Nicholas Biunno, Principal Engineer, Sanima-SCI, Inc.
6-TA3 Dielectric Material Properties: Essential Inputs to an Accurate Signal-Integrity Analysis and High-Reliability Design
Brian McDermott, Director, OEM Marketing and Design, Isola Group
Steve McKinney, Technical Marketing Engineer, Mentor Graphic
Track 7 | Chip and Board Interconnect Design
7-TA4 Effective Techniques for SERDES Channel Design
Panch Chandrasekaran, Connectivity Marketing Manager, Xilinx
Steve Baker, Senior High-Speed Architect, Mentor Graphics
7-TP1 Time-Domain Verification of Differential Transmission-Line Modeling Methods
Jonathan Coker, Principal Project Engineer, Mayo Clinic
Erik S. Daniel, Deputy Principal Engineer, Mayo Clinic
Barry Gilbert, Principal Investigator, Mayo Clinic
7-TP2 An Optimum Clocking Design with Frequency-Tabulated W-Element Interconnect Models
Woong Ryu, Staff Engineer, Intel Corporation
Min Wang, Senior Engineer, Intel Corporation
Ravindran Mohanavelu, Senior Engineer, Intel Corporation
7-WA1 Implementation of Broadband Transmission Line Models with Accurate Low-Frequency Response for High-Speed System Simulations
Woopoung Kim, SI/PI, Engineer Rambus, Inc.
Joong-Ho Kim, SI/PI Engineer, Rambus Inc.
Dan Oh, Singal Integrity Manager, Rambus Inc.
Chuck Yuan, SI/PI Manager, Rambus Inc.
7-WA2 Copper Media Transceivers Step Up to 10 Gbps
Lee Harrison, Vice President, Engineering, Keyeye Communications
7-WP1 A Co-Design Methodology of Signal Integrity and Power Integrity
Min Wang, Senior Engineer, Intel Corporation
Woong Hwan Ryu, Staff Engineer, Intel Corporation
7-WP2 Single-Port TDR Test for Calibrated Two-Port S-Parameters
James Mayrand, Complete DVT Solutions
Brian Shumaker, Complete DVT Solutions
Track 8 | Multi-Gigabit Backplane Interconnect Design
8-TA4 S-Parameter Characterization of Operational Transmitters and Channels in Digital Communications Systems
Greg Le Cheminant, Measurement Applications Engineer, Agilent Technologies
Marlin Viss, R&D Engineer, Agilent Technologies
8-TP1 Theory and Measurement of Unbalanced Differential-Mode Transmission Lines
Stephen Smith, Staff Signal-Integrity Engineer, FCI USA
Sedig Agili, Assistant Professor, Electrical Engineering, Penn State University
Vittal Balasubramanian, Senior Signal-Integrity Engineer, FCI USA
8-TP2 Attenuation in PCB Traces Due to Periodical Discontinuities
Jason Miller, Staff Engineer, Sun Microsystems
Gustavo Blando, Engineer, Sun Microsystems
Cheryl Preston, Staff Engineer, Sun Microsystems
Jim DeLap, Applications Engineer, Ansoft Corp.
Istvan Novak, Staff Engineer, Sun Microsystems
8-WA1 Advances in SMT Backplane Connectors
Phil Stokoe, Amphenol TCS
Burke Hunsaker, Amphenol TCS
Douglas Cannon, Amphenol TCS
8-WA2 Developing a "Physical" Model for Vias
Christian Schuster, Research Staff Member, IBM T.J. Watson Research Center
Young Kwark, Research Staff Member, IBM T.J. Watson Research Center
Giuseppe Selli, Intern, IBM T.J. Watson Research Center
Prathap Muthana, Intern, IBM T.J. Watson Research Center
8-WP1 Practical Design Considerations for 10- to 25-Gbps Backplane Copper Serial Links
Ravi Kollipara, Senior Principal Engineer, Rambus, Inc.
Frank Lambrecht, Senior Member of Technical Staff, Rambus, Inc.
Chuck Yuan, Engineering Manager, Rambus, Inc.
Jared Zerbe, Engineering Director, Rambus, Inc.
Gautam Patel, Amphenol TCS
Tom Cohen, Amphenol TCS
Brian Kirk, Amphenol TCS
8-WP2 Designing Scalable 10-Gbps Backplane Interconnect Systems Utilizing Advanced Verification Methodologies
Kevin Grundy, President and Chief Executive Officer, Silicon Pipe
Mike Resso, Business Development Manager, Agilent Technologies
Gary Otonari, Engineering Project Manager, GigaTest Labs
Haw-Jyh Liaw, Director of Systems, Aeluros
Track 9 | High-Speed Timing, Jitter, and Noise
9-TA1 Jitter Spectral Theory
Iliya Zamek
9-TA2 Anticipating, Characterizing, and Avoiding Problems with Crosstalk
Ransom Stephens, Research Scientist, Teraspeed Consulting Group
Al Neves, Senior Staff Engineer, Teraspeed Consulting Group
9-TA3 New Measurement and Analysis Methods For Higher-Order Phase-Locked Loop (PLL) Characterizations
Mike Li, Chief Technology Officer, Wavecrest
Jun Ma, Wavecrest Corporation
9-TA4 Group Delay and Its Impact on Serial Data Transmission and Testing
Peter Pupalaikis, Principal Technologist, LeCroy Corporation
9-TP1 Voltage Noise to Phase Jitter Conversion
Andrew Martwick, Intel Corporation
9-TP2 Analysis of Phase Noise Performance in Reference Clocks and Its Impact on Jitter in High-Speed Digital Communications
Jim Stimple, Department Scientist, Agilent Technologies
Greg Le Cheminant, Measurement Applications Engineer, Agilent Technologies
Track 10 | Coding and Signal Processing
10-WA1 Moving 10 Gigabit Ethernet onto UTP: Moving 10GE into a Volume Platform
Ramin Shirani, Vice President, Engineering, Aquantia
Bill Woodruff, Vice President, Marketing, Aquantia
10-WA2 An Analytic System Model for High-Speed Interconnects and Its Application to the Specification of Signaling and Equalization Architectures for 10-Gbps Backplane Transmission
Joseph Caroselli, Senior Manager, Systems Architecture, LSI Logic
Cathy Ye Liu, Principal Engineer, LSI Logic
10-WP1 Modeling and Mitigation of Error Propagation of Decision Feedback Equalization in High-Speed Backplane Transceivers
Cathy Liu, Principal Engineer, LSI Logic
Jose Caroselli, Senior Manager, Systems Architecture, LSI Logic
10-WP2 Error-Correction Coding in a Serial Digital Multi-Gigabit Communication System: Implementation and Results
David Carney, Senior Hardware Engineer, Plexus Corp.
Edward Chandler, Professor of EECS, Milwaukee School of Engineering
Track 11 | Passive Component Characterization
11-TA2 S-Parameter Characterization of Sockets
Stefaan Sercu, Manage SI Group, FCI
Willem Dalinghaus, Avans Hogeschool
Jan De Geest, R&D Engineer, SI Group, FCI
Dana Bergey, Manager, SI Group, FCI
11-TA3 Full-Wave Simulation and Validation of a Simple and Complex Via Structure
Bruce Archambeault, STSM, IBM
Samuel Connor, Senior Engineer, IBM
D.N. de Araujo, Engineer, IBM
A. Ruehli, IBM
Christian Schuster, IBM
M.R. Hashemi, Pennsylvania State University
R. Mitta, Pennsylvania State University
11-TA4 Slow-Wave Causal Model for Multilayer Ceramic Capacitors
Istvan Novak, Senior Signal-Integrity Engineer, Sun Microsystems
Gustavo Blando, Signal-Integrity Engineer, Sun Microsystems
Jason Miller, Staff Engineer, Sun Microsystems
11-TP2 Effects of InfiniBand Fixture Crosstalk on Synthesized Eye Diagram
Eugene Mayevskiy, Applications Engineer, Tektronix, Inc.
Track 12 | Power Integrity and EMC
12-TA1 EMC Simulation of Complex High-Performance PCBs and Shielding Effectiveness
Jack Parkes, Corporate Fellow, Ansoft Corporation
J. Eric Bracken, Corporate Fellow Ansoft Corporation
Zoltan Cendes, Founder, Chairman, and Chief Technology Officer Ansoft Corporation
12-TA2 Impedance Matched Lossy Decoupling for PCB Power Delivery and PCB/Heatsink Radiated EMI Noise
Xin Wu, Fluent, Inc.
12-TA3 Bypass Filter Design Considerations for Modern Digital Systems: A Comparative Evaluation of the Big "V", Multipole, and Many Pole Bypass Strategies
Steve Weir, Consultant, Teraspeed Consulting Group
12-TA4 Power-Integrity Analysis of DDR2 Memory Systems during Simultaneous Switching Events
Ralf Schmitt, Engineering Manager, Rambus, Inc.
Joong-Ho Kim, Signal-Integrity Engineer, Rambus, Inc.
Kyung Suk (Dan) Oh, Engineering Manager, Rambus, Inc.
Xingchao (Chuck) Yuan, Engineering Manager, Rambus, Inc.
12-WA1 Effective Modeling and Analysis of EMI Effects on Printed Circuit Boards
Kun Zhang, Huawei, Technologies
Yu Liu, School of Electronic Engineering,Xidian University
Zhen Mu, Cadence Design Systems, Inc.
12-WA2 Finding the Root Cause of an ESD Upset Event
David Pommerenke, Associate Professor, University Missouri-Rolla
Jayong Koo, Doctoral Student, University Missouri-Rolla
Giorgi Muchaidze, Doctoral Student, University Missouri-Rolla
12-WP2 Time- and Frequency-Domain Analysis of Decoupling Capacitor Distance on Printed Circuit Boards
Bruce Archambeault, STSM, IBM
Samuel Connor, Senior Engineer, IBM
Track 13 | Test Fixture Design
13-WA1 Practical Design and Implementation of Stripline TRL Calibration Fixtures for 10-Gigabit Interconnect Analysis
Dave Dunham, Electrical Engineering Manager, Molex, Inc.
Vince Duperron, Electrical Project Engineer, Molex, Inc.
Mike Resso, Business Development Manager, Agilent
13-WA2 Advanced Package Design and Validation Methods Using 9-ps TDR and 10-Gbps Active High-Speed Chip
Dong-Ho Han, Intel Corporation
Bao Shu Xu, Intel Corporation
Jaemin Shin, Intel Corporation
Grace Hu, Intel Corporation
He Jiangqi, Intel Corporation
13-WP1 PCB Loadboard Design Challenges for Multi-Gigabit Devices in Automated Test Applications
Jose Moreira, Senior Applications Consultant, Agilent Technologies
Ming Tsai, Hardware Development Engineer, Xilinx
Jonathan Kenton, Senior Test Technology Engineer, Intel Corporation
Heidi Barnes, High-Frequency Interface Board Designer, Agilent Technologies
Don Faller, Senior Consultant, Agilent Technologies
13-WP2 Accurate Calibration and Measurement of Non-Insertable Fixture in FPGA and ASIC Device Characterization
Hong Shi, MTS, Altera
Geping Liu, Altera
Alan Liu, Altera
Track 14 | Business and Engineering Impacts
14-WA1 The SPIRIT Standard: Solving the SoC Risk Paradox
Victor Berman, Group Marketing Director, Cadence Design Systems
Saverio Fazzari, Technical Marketing Director, Cadence Design Systems
14-WA2 IP Evaluation Strategies for ASIC Design and Management
Mobashar Yazdani, ASIC Program Manager, Global Operations, HP
Mike Stahl, Alliance Manager/Scientist, Enterprise Servers, HP
14-WP1 Innovation: Learning from the EDA Industry
Brian Bailey, Consultant, Brian Bailey Consulting
14-WP2 DAMA, the Key to Becoming a Fast and Global Electronics Innovator
Wolfgang Heinrichs, General Manager, Business Development, Europe and America, Zuken
Kent McLeroth, Vice President of Systems Engineering, Zuken
DesignCon Awards
A-TA1 DesignCon Award Paper, Presented at DesignCon East 2005: Standards-Compliant IP Design: Advantages, Problems, and Future Directions
Amir Hekmatpour, Senior Engineer, IBM
Kenneth J. Goodnow, Senior Engineer, IBM
A-TA2 DesignCon Award Paper, Presented at DesignCon East 2005: Creating Repeatable 10-Gbps Channels in an Uncertain World
Eric Montgomery, Signal-Integrity Engineer, Interconnect Technologies, Northrop Grumman
Rob Speer, Interconnect Technologies, Northrop Grumman
A-TA3 DesignCon Award Paper, Presented at Euro DesignCon 2005: At-Speed Scan Transition and Path Delay Testing Using On-Chip PLL for a High-Frequency Device and Low-Frequency Tester
Eric Haioun, Digital Designer and Principal Staff Engineer, Freescale Semiconductors
Colin Renfrew, Design Engineer, Freescale Semiconductors
Robert Gach, Design Manager, Freescale Semiconductors
A-TP1 DesignCon Award Paper, Presented at Euro DesignCon 2005: The Duobinary Format: A New Application for an Idea Published Long Ago
Hans-Joachim Goetz, Distinguished Member of Technical Staff, Lucent Technologies
Jeffrey H. Sinsky, Member of Technical Staff, Lucent Technologies
A-TP2 DesignCon Award Paper, Presented at Euro DesignCon 2005: A Flexible and Adaptive Pipelining Concept for Low-Latency Interconnects
Markus Buehler, Methodology Engineer, IBM
A-WP1 DesignCon Award Paper, Presented at Euro DesignCon 2005: Challenges in Power PC440 - FS Soft Core Development: Timing Perspective
Terry Biggs, Project Manager, Hewlett-Packard
Ken Umino, Staff Design Consultant, Synopsys Inc.
Kaijian Shi, Principal Consultant, Synopsys, Inc.
TecPreviews
TP-TA1.2 The More Speed, the Less Haste: Make Your Pull-Based On-Line Marketing Campaign Truly Reactive
TP-TA3.1 65 nm CMOS Process Technology
TP-TA3.2 BGA Ground Ball Placement
TP-TA4.1 Dual-Dirac, Scope Histograms, and BERTScan Measurements
TP-TA4.2 IBIS Connector Models: Do They Exist?
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